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HD74HC175
Quad. D-type Flip-Flops (with Clear)
REJ03D0585-0300 Rev.3.00 Jan 31, 2006
Description
Information at the D inputs of the HD74HC175 is transferred to the Q and Q outputs on the positive going edge of the clock pulse. Both true and compliment outputs from each flip-flop are externally available. All four flip-flops are controlled by a common clock and a common clear. Clearing is accomplished by a negative pulse at the clear input. All four Q outputs are cleared to a logic low level and all four Q outputs to a logic high level.
Features
* * * * * * High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HC175P Package Type DILP-16 pin Package Code (Previous Code) Package Abbreviation -- ELL (2,000 pcs/reel) Taping Abbreviation (Quantity)
PRDP0016AE-B P (DP-16FV) PTSP0016JB-A HD74HC175TELL TSSOP-16 pin T (TTP-16DAV) Note: Please consult the sales office for the above package availability.
Function Table
Clear L H H H High level Low level Irrelevant Inputs Clock X Output D X H L X Q L H L no change Q H L H
L
H: L: X:
Rev.3.00, Jan 31, 2006 page 1 of 6
HD74HC175
Pin Arrangement
Clear 1 1Q 2 1Q 3 1D 4 2D 5 2Q 6 2Q 7 GND 8 (Top view)
D CK Q CLR Q D Q CK CLR Q Q CLR CK Q D CLR Q CK Q D
16 VCC 15 4Q 14 4Q 13 4D 12 3D 11 3Q 10 3Q 9 Clock
Logic Diagram
1D D CK Clock 2D CK CL D CK CK CL 3D D CK CK CL 4D D CK CK CL Clear 4Q Q 3Q Q 2Q Q 1Q 2Q Q 1Q
3Q
4Q
Rev.3.00, Jan 31, 2006 page 2 of 6
HD74HC175
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 -65 to +150 Unit V V mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Note: Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Unit V V C ns Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 V Test Conditions
VIL
V
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
VOL
V
Vin = VIH or VIL
IOH = -4 mA IOH = -5.2 mA IOL = 20 A
Input current Quiescent supply current
Iin ICC
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Rev.3.00, Jan 31, 2006 page 3 of 6
HD74HC175
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Ta = 25C Ta = -40 to +85C Unit Min Typ Max Min Max -- -- -- -- -- -- -- -- -- 100 20 17 5 5 5 100 20 17 80 16 14 -- -- -- -- -- -- -- -- 14 -- -- 14 -- -- 3 - -- -1 -- -- -1 -- -- 9 -- -- 5 -- 5 6 30 35 150 30 26 185 37 31 -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 -- -- -- -- -- -- -- -- -- 125 25 21 5 5 5 125 25 21 100 20 17 -- -- -- -- 5 24 28 190 38 33 230 46 39 -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10 MHz Test Conditions
tPLH, tPHL
ns
Clock to Q or Q
ns
Clear to Q or Q
Setup time
tsu
ns
Data to Clock
Hold time
th
ns
Clock to Data
Removal time
trem
ns
Clear to Clock
Pulse width
tw
ns
Clock, Clear
Output rise/fall time Input capacitance
tTLH, tTHL
ns
Cin
pF
Test Circuit
Measurement point
CL*
Note: CL includes the probe and fig capacitance.
Rev.3.00, Jan 31, 2006 page 4 of 6
HD74HC175
Waveforms
* Waveform - 1
tr
90 % 50 % 10 % 90 % 50 % 10 % 50 %
tf VCC 0V
Data
t su tr Clock
10 %
th tf
90 % 50 % 50 % 10 %
t su
th
VCC
50 %
tw t PLH Q
10 % 90 % 50 %
tw t PHL
90 % 50 % 10 %
0V
VOH VOL
t PHL Q
t TLH
t PLH
50 % 10 %
t THL
90 %
VOH VOL
50 % 10 %
t THL
t TLH
* Waveform - 2
90 % 50 % 10 %
tf
tr 90 % 50 % 10 % tw tf 90 % 50 % 10 % tw 90 % 50 % 10 % t THL t PLH 90 % tr 90 % 50 % 10 % t PLH 90 % 50 % 10 % t TLH t PHL 90 % 50 % 10 % t THL VOH VOL VOL VOH VCC 0V VCC 0V
Clear
Clock
t rem t PHL Q
Q
50 % 10 % t TLH Note : Clock Input : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns Data Input : PRR 500 kHz
Rev.3.00, Jan 31, 2006 page 5 of 6
HD74HC175
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-TSSOP16-4.4x5-0.65
RENESAS Code PTSP0016JB-A
Previous Code TTP-16DAV
MASS[Typ.] 0.05g
*1
D F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
16
9
bp
*2
HE
E
c
Reference Symbol
Dimension in Millimeters Min Nom 5.0 4.40 Max 5.3
Index mark
Terminal cross section ( Ni/Pd/Au plating )
D E A2 A1 0.03
0.07
0.10 1.10
1 Z e
*3
8 bp L1 x M
A bp b1 c c
1
0.15
0.20
0.25
0.10
0.15
0.20
A
HE
0 6.20 6.40 0.65
8 6.60
A1
L
e x y
0.13 0.10 0.65 0.4
1
y
Detail F
Z L L 0.5 1.0
0.6
Rev.3.00, Jan 31, 2006 page 6 of 6
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